The present disclosure relates generally to the field of fabrication of semiconductor devices, and more specifically to a method of fabricating a fin-type field effect transistor (finFET) or a fully depleted silicon on insulator (FDSOI) device, or a portion thereof.
Double-gate metal-oxide semiconductor field-effect transistors (MOSFETs) are MOSFETs that incorporate two gates into a single device. Some of these devices may be known as finFETs when their structure includes a thin “fin” extending from a substrate. Planar versions of the double-gate MOSFETs also exist without the fin. Silicon based finFETs have been successfully fabricated using conventional MOSFET technology. A typical finFET is fabricated on a substrate with an overlying insulating layer with a thin ‘fin’ extending from the substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. The double gate is beneficial in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of finFETs include reducing the short channel effect and higher current flow. Other finFET architectures may include three or more effective gates.
FinFET and fully depleted planar SOI devices are particularly attractive as an alternative to conventional planar bulk CMOS devices because improved gate control with thin Si films and two gates enables aggressive scaling of the device dimensions without significant penalties in terms of static leakage, short-channel effects or performance degradation. FinFETs can be made using bulk technology. However, further scaling of conventional planar bulk CMOS devices is difficult below about 45 nm technology.
However, a significant obstacle to manufacturing finFETs and FDSOI MOSFETs is the very small dimensions required for the fin or Si film in order to benefit from the thin film architecture. For example, this may be a gate-length ˜⅓ for finFETs and a gate-length ˜¼ for single-gate FDSOI. Thus, for a device with a 30 nm width, a 10 nm fin or 7 nm Si film is needed. This target can be achieved but the variations in device performance, due to variations around the nominal value, would be so large that circuit designs would not benefit from the nominal performance because the designers would need to fix the clock frequency according to the delay of the worst-case device. Furthermore, device performance is limited by carrier scattering due to the roughness of the conducting interfaces. This is a well-understood and unavoidable effect in planar bulk devices and is also present in thin-film devices.
As such, an improved semiconductor device and fabrication method of the same is desired.